Intel and AMD CPUs have different modes/states known as C-States and denoted as Cn or CnE. High values of n imply a deeper sleep. The 'E' denotes enhancements to the sleep state.
C0 - is the normal state, when the CPU is awake and fully functional.
These states involve cutting the clock signal or reducing the voltage to different components of the CPU. The CPU takes longer to wake up from a higher level sleep state compared to a lower level state, as more components need to be bought back i.e. restored clock signal or increase voltage or both.
C1 - x86 enters this state using the HLT (halt) instruction and wakes up when it receives an interrupt. Clock signal is stopped for all components of the CPU, except two (APIC and bus interface). This leads to lower power consumption.
C1E - similar to C1 with the additional reduction of voltage. This is setup in the BIOS, the system will either enter C1 or C1E state when a HLT instruction is executed.
The CPU can temporarily exit the C1 or C1E states, when an interrupt arrives, service the request and return back to either of these two low power modes. The state the CPU enters to service the interrupt is known as the Snoop State. In snoop state the clock is fully restored, however voltage is kept at a lower state when the bios is configured for C1E.
C2 Stop Grant - similar to C1, except there is no software HLT instruction to activate this state, instead there is an additional stop clock pin STPCLK which has to be activated. The clock signal is stopped for all components of the CPU, except APIC and bus interface. The clock generator chip (Phased-Locked Loop) is active (for APIC and bus interface) and generating the external CPU clock. The CPU can temporarily awaken and handle interrupt requests, this state is known as the Stop Clock Snoop State.
C2 Stop Clock - similar to C2 Stop Grant and additionally the clock generator chip is stopped. This state has been moved to C3 in recent CPUs.
C2E Stop Grant - with the additional reduction of CPU voltage. Configured in the BIOS, the CPU will either enter the C2 Stop Grant or C2E Stop Grant state.
C3 - clock signal is stopped for all components, including APIC and bus controller, thus the CPU can't respond to any interrupts. The state is activated through the SLP (or DPSLP) pin, when the CPU is in C2 state i.e. the CPU switches from C2 to C3 states by first activating STPCLK and then SLP/DPSLP. AMD CPUs enter this state through two different mechanisms. Its also referred to as Deep Sleep State.
C4 - this state is entered from C3 state and reduces the CPU voltage consumption. This was developed for mobile processors. Its also referred to as Deeper Sleep State.
C4E - in this state the CPU voltage is further reduced by disabling the L2 memory cache. It is also referred to as C5.
C6 - this state is entered from the C4 state. In this state the CPU saves its state in static RAM and the CPU voltage can be reduced to as low as zero. The static RAM is powered separately. Waking up the CPU takes longer but not as much as turning on the computer. This is also referred to as Deep Power Down.
Further enhancements in processors are leading towards separating out the power source/control units for various parts of the CPU, thus allowing some cores to be shutdown or sent to C6 state while other cores are active.
C0 - is the normal state, when the CPU is awake and fully functional.
These states involve cutting the clock signal or reducing the voltage to different components of the CPU. The CPU takes longer to wake up from a higher level sleep state compared to a lower level state, as more components need to be bought back i.e. restored clock signal or increase voltage or both.
C1 - x86 enters this state using the HLT (halt) instruction and wakes up when it receives an interrupt. Clock signal is stopped for all components of the CPU, except two (APIC and bus interface). This leads to lower power consumption.
C1E - similar to C1 with the additional reduction of voltage. This is setup in the BIOS, the system will either enter C1 or C1E state when a HLT instruction is executed.
The CPU can temporarily exit the C1 or C1E states, when an interrupt arrives, service the request and return back to either of these two low power modes. The state the CPU enters to service the interrupt is known as the Snoop State. In snoop state the clock is fully restored, however voltage is kept at a lower state when the bios is configured for C1E.
C2 Stop Grant - similar to C1, except there is no software HLT instruction to activate this state, instead there is an additional stop clock pin STPCLK which has to be activated. The clock signal is stopped for all components of the CPU, except APIC and bus interface. The clock generator chip (Phased-Locked Loop) is active (for APIC and bus interface) and generating the external CPU clock. The CPU can temporarily awaken and handle interrupt requests, this state is known as the Stop Clock Snoop State.
C2 Stop Clock - similar to C2 Stop Grant and additionally the clock generator chip is stopped. This state has been moved to C3 in recent CPUs.
C2E Stop Grant - with the additional reduction of CPU voltage. Configured in the BIOS, the CPU will either enter the C2 Stop Grant or C2E Stop Grant state.
C3 - clock signal is stopped for all components, including APIC and bus controller, thus the CPU can't respond to any interrupts. The state is activated through the SLP (or DPSLP) pin, when the CPU is in C2 state i.e. the CPU switches from C2 to C3 states by first activating STPCLK and then SLP/DPSLP. AMD CPUs enter this state through two different mechanisms. Its also referred to as Deep Sleep State.
C4 - this state is entered from C3 state and reduces the CPU voltage consumption. This was developed for mobile processors. Its also referred to as Deeper Sleep State.
C4E - in this state the CPU voltage is further reduced by disabling the L2 memory cache. It is also referred to as C5.
C6 - this state is entered from the C4 state. In this state the CPU saves its state in static RAM and the CPU voltage can be reduced to as low as zero. The static RAM is powered separately. Waking up the CPU takes longer but not as much as turning on the computer. This is also referred to as Deep Power Down.
Further enhancements in processors are leading towards separating out the power source/control units for various parts of the CPU, thus allowing some cores to be shutdown or sent to C6 state while other cores are active.
