There are various technologies in the evolution of memory chips. The commonly used standard is Synchronous Dynamic Random Access Memory. These chips are synchronized to a time source.
Most common memory chips are of type DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM. DDR stands for Double Data Rate i.e. two data chunks are transferred every clock cycle. The manufacturers market these chips as DDR-nnn where nnn is double the clock frequency i.e. DDR2-800 can run at a maximum of 400MHz, DDR3-1333 can run at a maximum of 666.6MHz. The advertised frequency is double the actual value since two data chunks are transferred in every cycle.
These memory chips are connected to (soldered on) memory modules which have their own specifications of the form PCn-mmmm, where n is the generation and mmmm is the maximum bandwidth (bytes transferred per second). PC2-6400 implies second generation, 6400MB/sec.
The memory chip and memory module should have compatible specifications to achieve the maximum efficiency e.g. DDR2-800 memory chip can transfer -
400MHz (clock speed) * 2 (two transfers every cycle) * 64 bits (bits in a transfer) / 8 (bits per byte) = 6400 bytes/second
this chip should be paired with a PC2-6400 module. The generation of memory chip 2 for DDR2 should match with generation of the module i.e. 2 for PC2.
The specifications of the chips and modules are their maximum values and these are not always achieved - since there are other commands/information that is transferred to make the data transfer happen.
Between DDR, DDR2 and DDR3 there is a difference in power consumptions, DDR3 operates at a lower voltage compared to DDR2, which operates at a lower voltage compared to DDR.
There are many types of latencies in a memory chip. CAS Latency (CL) is the commonly referred metric. This is the amount of delay between a request and until data is delivered. Generally DDR is fastest, followed by DDR2 and then DDR3. Two memory chips of different generations and same frequency - DDR2-800 CL5 and DDR3-800 CL7 - offer different latencies of 5 and 7 clock cycles, in this case DDR2-800 CL5 is faster than DDR3-800 CL7. If the clock frequencies are different then the cycle duration is smaller and in this case the 7 cycle count time may be smaller than the 5 cycle count time.
There are other latencies apart from CL. RAM manufacturers mention these latenices as a-b-c-d e.g. 3-5-5-15.
a- is the CAS Latency - time between command sent and data received.
b - RAS to CAS - time between activation of line and column.
c - RAS Precharge - time between access to another line of data
d - Active to Precharge - time between two accesses
Another latency is sometimes mentioned, the time it takes for the memory chip to be ready to accept the first command.
The memory chips have an internal clock which transfers data from the memory array to the I/O buffer. The transfer from I/O buffer to memory controller is based on the external clock. The nnn of DDR-nnn specification is the external clock frequency. The internal clock frequency is doubled in every generation i.e. DDR transfers 2 bits, DDR2 transfers 4 bits and DDR3 transfers 8 bits on every internal clock cycle. Thus DDR-400 and DDR2-400 both transfer at an external clock of 200MHz but internally the DDR-400 will use a 200MHz clock whereas the DDR2-400 will use a 100MHz clock. The increase of internal data transfer rate allows subsequent generations of DDR chips to support a higher external clock speed i.e. DDR-400, DDR2-800 and DDR3-1600 have the same internal clock speed of 200MHz.
The memory module connects to memory controllers, which are either embedded on the CPUs or are separate chips on the north bridge. Its possible to connect multiple memory modules on to one memory controller using one or more channels. A single channel connection has 64-bit data bus between the controller and the module(s).
In a dual channel configuration, the memory controller will have a 128-bit data bus, the fist 64-bits connect to module 1 and the second 64-bits connect to module2. Triple channel configuration will have 192-bit data bus connecting the memory controller to three memory modules and Quad channel has a 256-bit data bus.
Memory overclocking allows changing the frequency of the external clock of the memory module. This feature is provided by the motherboard, some low-end boards don't have this feature, some boards offer a method called Synchronous and some high-end boards offer a method called Asynchronous. Synchronous overclocking ties the memory clock to the CPU external clock and Asynchronous overclocking allows an independent configuration.
Alternative methods to memory overclocking involves increasing the voltage of the memory module or changing the memory latency timings.
Most common memory chips are of type DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM. DDR stands for Double Data Rate i.e. two data chunks are transferred every clock cycle. The manufacturers market these chips as DDR-nnn where nnn is double the clock frequency i.e. DDR2-800 can run at a maximum of 400MHz, DDR3-1333 can run at a maximum of 666.6MHz. The advertised frequency is double the actual value since two data chunks are transferred in every cycle.
These memory chips are connected to (soldered on) memory modules which have their own specifications of the form PCn-mmmm, where n is the generation and mmmm is the maximum bandwidth (bytes transferred per second). PC2-6400 implies second generation, 6400MB/sec.
The memory chip and memory module should have compatible specifications to achieve the maximum efficiency e.g. DDR2-800 memory chip can transfer -
400MHz (clock speed) * 2 (two transfers every cycle) * 64 bits (bits in a transfer) / 8 (bits per byte) = 6400 bytes/second
this chip should be paired with a PC2-6400 module. The generation of memory chip 2 for DDR2 should match with generation of the module i.e. 2 for PC2.
The specifications of the chips and modules are their maximum values and these are not always achieved - since there are other commands/information that is transferred to make the data transfer happen.
Between DDR, DDR2 and DDR3 there is a difference in power consumptions, DDR3 operates at a lower voltage compared to DDR2, which operates at a lower voltage compared to DDR.
There are many types of latencies in a memory chip. CAS Latency (CL) is the commonly referred metric. This is the amount of delay between a request and until data is delivered. Generally DDR is fastest, followed by DDR2 and then DDR3. Two memory chips of different generations and same frequency - DDR2-800 CL5 and DDR3-800 CL7 - offer different latencies of 5 and 7 clock cycles, in this case DDR2-800 CL5 is faster than DDR3-800 CL7. If the clock frequencies are different then the cycle duration is smaller and in this case the 7 cycle count time may be smaller than the 5 cycle count time.
There are other latencies apart from CL. RAM manufacturers mention these latenices as a-b-c-d e.g. 3-5-5-15.
a- is the CAS Latency - time between command sent and data received.
b - RAS to CAS - time between activation of line and column.
c - RAS Precharge - time between access to another line of data
d - Active to Precharge - time between two accesses
Another latency is sometimes mentioned, the time it takes for the memory chip to be ready to accept the first command.
The memory chips have an internal clock which transfers data from the memory array to the I/O buffer. The transfer from I/O buffer to memory controller is based on the external clock. The nnn of DDR-nnn specification is the external clock frequency. The internal clock frequency is doubled in every generation i.e. DDR transfers 2 bits, DDR2 transfers 4 bits and DDR3 transfers 8 bits on every internal clock cycle. Thus DDR-400 and DDR2-400 both transfer at an external clock of 200MHz but internally the DDR-400 will use a 200MHz clock whereas the DDR2-400 will use a 100MHz clock. The increase of internal data transfer rate allows subsequent generations of DDR chips to support a higher external clock speed i.e. DDR-400, DDR2-800 and DDR3-1600 have the same internal clock speed of 200MHz.
The memory module connects to memory controllers, which are either embedded on the CPUs or are separate chips on the north bridge. Its possible to connect multiple memory modules on to one memory controller using one or more channels. A single channel connection has 64-bit data bus between the controller and the module(s).
In a dual channel configuration, the memory controller will have a 128-bit data bus, the fist 64-bits connect to module 1 and the second 64-bits connect to module2. Triple channel configuration will have 192-bit data bus connecting the memory controller to three memory modules and Quad channel has a 256-bit data bus.
Memory overclocking allows changing the frequency of the external clock of the memory module. This feature is provided by the motherboard, some low-end boards don't have this feature, some boards offer a method called Synchronous and some high-end boards offer a method called Asynchronous. Synchronous overclocking ties the memory clock to the CPU external clock and Asynchronous overclocking allows an independent configuration.
Alternative methods to memory overclocking involves increasing the voltage of the memory module or changing the memory latency timings.
